A conventional 2-to-4 address decode scheme can have two inputs IN0 and IN1 sent to two latches to produce latched outputs. The latched outputs can be inputs to NAND gates to produce 1 active output out of the 4 outputs. For performance, it is important to reduce the delay through the latches. This can be done by reducing the number of logic stages needed to produce the latched outputs.
It would be desirable to implement a split decode latch with shared feedback.